1. Field of the Invention
The present invention is related to circuit modeling methods and software, and more particularly to logic circuit modeling methods and software that compute loading effects on logical circuit block signal performance.
2. Description of Related Art
Circuit modeling methods, typically implemented in software tools that simulate the performance of circuits for design verification provide a mechanism for optimizing and ensuring proper performance of Integrated Circuits (IC) including Very-Large-Scale Integrated (VLSI) circuits. Logical circuits are typically represented as circuit blocks having a modeled response to input state changes. In response to an input change, a delay time and a transition time are generally used to generate the output voltage of the logical circuit block within the model.
The transition time and delay time of a logical circuit block vary over various parameters of the circuit block, such as output transistor size, power supply voltage and temperature. The transition time and delay time may also be modeled in terms of input voltage swing and transition time. Existing models take all or some of the above factors into account in order to determine the output signal produced by a logical circuit block.
Additionally, output loading characteristics have a large effect on the output signal and various techniques have been developed within present circuit models and modeling software to take loading effects into account. The simplest model used in present simulation tools is a lumped capacitance coupled to the output of the logical circuit block. The lumped capacitance represents all of the loading capacitance connected to the output of the logical circuit block, and may in the simplest case be equal to all of the capacitance connected to the logical circuit block output, or may be a capacitance value determined by sophisticated models of the interconnect resistance and capacitances at various points in the circuits connected to the output of the logical circuit block.
The above-referenced patent application describes a pi-network model that includes two capacitors determined from distributed capacitances connected to the output of a logical circuit block, along with the effects of the wire resistances connecting the capacitances. The pi-network model provides an improved calculation of the effects of distributed capacitances connected to the output of the logical circuit block.
However, present circuit models have progressively reduced accuracy as the logical circuit block output loading capacitance becomes dominated by transistor gate capacitances. Since the load on the output of a logical circuit block is typically at least one logical gate input connected via a typically low-resistance interconnect, the transistor gate capacitance, which is not in actuality a linear capacitance but a non-linear capacitance that varies with output signal voltage, has a significant impact on the logical circuit block transition time and delay time. The non-linear nature of the loading gate capacitances causes the transition time and delay time to diverge from values predicted by a simple capacitive model, making a simple shunt capacitance load model or fixed capacitive network load model ineffective for predicting both the transition time and delay time of a logical circuit block.
However, modeling gate capacitance loading effects on a circuit output is a complicated simulation task, as logical circuit block performance must be modeled over the complete range of device sizes that are encountered in actual designs. Transistor device size (and hence gate capacitance) is typically a static value in designs simulated by circuit simulation tools such as SPICE.
Therefore, it would be desirable to provide modeling methods and modeling software that accurately predict the performance of a logical circuit block as the logical circuit block output load varies between predominantly transistor gate capacitance and predominantly wire capacitance. It would further be desirable to predict non-linear effects of logical circuit block loading on logical circuit block transition time and delay time. It would further be desirable to provide a method for determining characteristics of the logical circuit block without having to model the logical circuit block over loading circuit transistor device size changes.